
rgb888:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004005d0 <_init>:
  4005d0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4005d4:	910003fd 	mov	x29, sp
  4005d8:	94000044 	bl	4006e8 <call_weak_fn>
  4005dc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4005e0:	d65f03c0 	ret

Disassembly of section .plt:

00000000004005f0 <.plt>:
  4005f0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4005f4:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x10174>
  4005f8:	f947fe11 	ldr	x17, [x16, #4088]
  4005fc:	913fe210 	add	x16, x16, #0xff8
  400600:	d61f0220 	br	x17
  400604:	d503201f 	nop
  400608:	d503201f 	nop
  40060c:	d503201f 	nop

0000000000400610 <perror@plt>:
  400610:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400614:	f9400211 	ldr	x17, [x16]
  400618:	91000210 	add	x16, x16, #0x0
  40061c:	d61f0220 	br	x17

0000000000400620 <open@plt>:
  400620:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400624:	f9400611 	ldr	x17, [x16, #8]
  400628:	91002210 	add	x16, x16, #0x8
  40062c:	d61f0220 	br	x17

0000000000400630 <__libc_start_main@plt>:
  400630:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400634:	f9400a11 	ldr	x17, [x16, #16]
  400638:	91004210 	add	x16, x16, #0x10
  40063c:	d61f0220 	br	x17

0000000000400640 <close@plt>:
  400640:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400644:	f9400e11 	ldr	x17, [x16, #24]
  400648:	91006210 	add	x16, x16, #0x18
  40064c:	d61f0220 	br	x17

0000000000400650 <__gmon_start__@plt>:
  400650:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400654:	f9401211 	ldr	x17, [x16, #32]
  400658:	91008210 	add	x16, x16, #0x20
  40065c:	d61f0220 	br	x17

0000000000400660 <write@plt>:
  400660:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400664:	f9401611 	ldr	x17, [x16, #40]
  400668:	9100a210 	add	x16, x16, #0x28
  40066c:	d61f0220 	br	x17

0000000000400670 <abort@plt>:
  400670:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400674:	f9401a11 	ldr	x17, [x16, #48]
  400678:	9100c210 	add	x16, x16, #0x30
  40067c:	d61f0220 	br	x17

0000000000400680 <read@plt>:
  400680:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400684:	f9401e11 	ldr	x17, [x16, #56]
  400688:	9100e210 	add	x16, x16, #0x38
  40068c:	d61f0220 	br	x17

0000000000400690 <printf@plt>:
  400690:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400694:	f9402211 	ldr	x17, [x16, #64]
  400698:	91010210 	add	x16, x16, #0x40
  40069c:	d61f0220 	br	x17

Disassembly of section .text:

00000000004006a0 <_start>:
  4006a0:	d280001d 	mov	x29, #0x0                   	// #0
  4006a4:	d280001e 	mov	x30, #0x0                   	// #0
  4006a8:	aa0003e5 	mov	x5, x0
  4006ac:	f94003e1 	ldr	x1, [sp]
  4006b0:	910023e2 	add	x2, sp, #0x8
  4006b4:	910003e6 	mov	x6, sp
  4006b8:	580000c0 	ldr	x0, 4006d0 <_start+0x30>
  4006bc:	580000e3 	ldr	x3, 4006d8 <_start+0x38>
  4006c0:	58000104 	ldr	x4, 4006e0 <_start+0x40>
  4006c4:	97ffffdb 	bl	400630 <__libc_start_main@plt>
  4006c8:	97ffffea 	bl	400670 <abort@plt>
  4006cc:	00000000 	.inst	0x00000000 ; undefined
  4006d0:	0040079c 	.word	0x0040079c
  4006d4:	00000000 	.word	0x00000000
  4006d8:	00400b80 	.word	0x00400b80
  4006dc:	00000000 	.word	0x00000000
  4006e0:	00400c00 	.word	0x00400c00
  4006e4:	00000000 	.word	0x00000000

00000000004006e8 <call_weak_fn>:
  4006e8:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x10174>
  4006ec:	f947f000 	ldr	x0, [x0, #4064]
  4006f0:	b4000040 	cbz	x0, 4006f8 <call_weak_fn+0x10>
  4006f4:	17ffffd7 	b	400650 <__gmon_start__@plt>
  4006f8:	d65f03c0 	ret
  4006fc:	00000000 	.inst	0x00000000 ; undefined

0000000000400700 <deregister_tm_clones>:
  400700:	d0000080 	adrp	x0, 412000 <perror@GLIBC_2.17>
  400704:	91016000 	add	x0, x0, #0x58
  400708:	d0000081 	adrp	x1, 412000 <perror@GLIBC_2.17>
  40070c:	91016021 	add	x1, x1, #0x58
  400710:	eb00003f 	cmp	x1, x0
  400714:	540000a0 	b.eq	400728 <deregister_tm_clones+0x28>  // b.none
  400718:	90000001 	adrp	x1, 400000 <_init-0x5d0>
  40071c:	f9461021 	ldr	x1, [x1, #3104]
  400720:	b4000041 	cbz	x1, 400728 <deregister_tm_clones+0x28>
  400724:	d61f0020 	br	x1
  400728:	d65f03c0 	ret
  40072c:	d503201f 	nop

0000000000400730 <register_tm_clones>:
  400730:	d0000080 	adrp	x0, 412000 <perror@GLIBC_2.17>
  400734:	91016000 	add	x0, x0, #0x58
  400738:	d0000081 	adrp	x1, 412000 <perror@GLIBC_2.17>
  40073c:	91016021 	add	x1, x1, #0x58
  400740:	cb000021 	sub	x1, x1, x0
  400744:	9343fc21 	asr	x1, x1, #3
  400748:	8b41fc21 	add	x1, x1, x1, lsr #63
  40074c:	9341fc21 	asr	x1, x1, #1
  400750:	b40000a1 	cbz	x1, 400764 <register_tm_clones+0x34>
  400754:	90000002 	adrp	x2, 400000 <_init-0x5d0>
  400758:	f9461442 	ldr	x2, [x2, #3112]
  40075c:	b4000042 	cbz	x2, 400764 <register_tm_clones+0x34>
  400760:	d61f0040 	br	x2
  400764:	d65f03c0 	ret

0000000000400768 <__do_global_dtors_aux>:
  400768:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40076c:	910003fd 	mov	x29, sp
  400770:	f9000bf3 	str	x19, [sp, #16]
  400774:	d0000093 	adrp	x19, 412000 <perror@GLIBC_2.17>
  400778:	39416260 	ldrb	w0, [x19, #88]
  40077c:	35000080 	cbnz	w0, 40078c <__do_global_dtors_aux+0x24>
  400780:	97ffffe0 	bl	400700 <deregister_tm_clones>
  400784:	52800020 	mov	w0, #0x1                   	// #1
  400788:	39016260 	strb	w0, [x19, #88]
  40078c:	f9400bf3 	ldr	x19, [sp, #16]
  400790:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400794:	d65f03c0 	ret

0000000000400798 <frame_dummy>:
  400798:	17ffffe6 	b	400730 <register_tm_clones>

000000000040079c <main>:
  40079c:	a9b27bfd 	stp	x29, x30, [sp, #-224]!
  4007a0:	910003fd 	mov	x29, sp
  4007a4:	a90153f3 	stp	x19, x20, [sp, #16]
  4007a8:	a9025bf5 	stp	x21, x22, [sp, #32]
  4007ac:	a90363f7 	stp	x23, x24, [sp, #48]
  4007b0:	a9046bf9 	stp	x25, x26, [sp, #64]
  4007b4:	f9002bfb 	str	x27, [sp, #80]
  4007b8:	b9006fa0 	str	w0, [x29, #108]
  4007bc:	f90033a1 	str	x1, [x29, #96]
  4007c0:	910003e0 	mov	x0, sp
  4007c4:	aa0003fb 	mov	x27, x0
  4007c8:	b9406fa0 	ldr	w0, [x29, #108]
  4007cc:	7100081f 	cmp	w0, #0x2
  4007d0:	54000060 	b.eq	4007dc <main+0x40>  // b.none
  4007d4:	12800000 	mov	w0, #0xffffffff            	// #-1
  4007d8:	140000e1 	b	400b5c <main+0x3c0>
  4007dc:	f94033a0 	ldr	x0, [x29, #96]
  4007e0:	91002000 	add	x0, x0, #0x8
  4007e4:	f9400000 	ldr	x0, [x0]
  4007e8:	52800001 	mov	w1, #0x0                   	// #0
  4007ec:	97ffff8d 	bl	400620 <open@plt>
  4007f0:	b900d7a0 	str	w0, [x29, #212]
  4007f4:	b940d7a0 	ldr	w0, [x29, #212]
  4007f8:	3100041f 	cmn	w0, #0x1
  4007fc:	540000c1 	b.ne	400814 <main+0x78>  // b.any
  400800:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400804:	9130c000 	add	x0, x0, #0xc30
  400808:	97ffff82 	bl	400610 <perror@plt>
  40080c:	12800020 	mov	w0, #0xfffffffe            	// #-2
  400810:	140000d3 	b	400b5c <main+0x3c0>
  400814:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400818:	91312000 	add	x0, x0, #0xc48
  40081c:	52803fe2 	mov	w2, #0x1ff                 	// #511
  400820:	52804841 	mov	w1, #0x242                 	// #578
  400824:	97ffff7f 	bl	400620 <open@plt>
  400828:	b900d3a0 	str	w0, [x29, #208]
  40082c:	b940d3a0 	ldr	w0, [x29, #208]
  400830:	7100001f 	cmp	w0, #0x0
  400834:	540000ca 	b.ge	40084c <main+0xb0>  // b.tcont
  400838:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  40083c:	91316000 	add	x0, x0, #0xc58
  400840:	97ffff74 	bl	400610 <perror@plt>
  400844:	12800040 	mov	w0, #0xfffffffd            	// #-3
  400848:	140000c5 	b	400b5c <main+0x3c0>
  40084c:	9101e3a0 	add	x0, x29, #0x78
  400850:	d28006c2 	mov	x2, #0x36                  	// #54
  400854:	aa0003e1 	mov	x1, x0
  400858:	b940d7a0 	ldr	w0, [x29, #212]
  40085c:	97ffff89 	bl	400680 <read@plt>
  400860:	b900cfa0 	str	w0, [x29, #204]
  400864:	3941e3a0 	ldrb	w0, [x29, #120]
  400868:	2a0003e1 	mov	w1, w0
  40086c:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400870:	9131c000 	add	x0, x0, #0xc70
  400874:	97ffff87 	bl	400690 <printf@plt>
  400878:	3941e7a0 	ldrb	w0, [x29, #121]
  40087c:	2a0003e1 	mov	w1, w0
  400880:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400884:	91324000 	add	x0, x0, #0xc90
  400888:	97ffff82 	bl	400690 <printf@plt>
  40088c:	b847a3a1 	ldur	w1, [x29, #122]
  400890:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400894:	9132c000 	add	x0, x0, #0xcb0
  400898:	97ffff7e 	bl	400690 <printf@plt>
  40089c:	7940ffa0 	ldrh	w0, [x29, #126]
  4008a0:	2a0003e1 	mov	w1, w0
  4008a4:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  4008a8:	91334000 	add	x0, x0, #0xcd0
  4008ac:	97ffff79 	bl	400690 <printf@plt>
  4008b0:	794103a0 	ldrh	w0, [x29, #128]
  4008b4:	2a0003e1 	mov	w1, w0
  4008b8:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  4008bc:	9133c000 	add	x0, x0, #0xcf0
  4008c0:	97ffff74 	bl	400690 <printf@plt>
  4008c4:	b84823a1 	ldur	w1, [x29, #130]
  4008c8:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  4008cc:	91344000 	add	x0, x0, #0xd10
  4008d0:	97ffff70 	bl	400690 <printf@plt>
  4008d4:	b84863a1 	ldur	w1, [x29, #134]
  4008d8:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  4008dc:	9134c000 	add	x0, x0, #0xd30
  4008e0:	97ffff6c 	bl	400690 <printf@plt>
  4008e4:	b848a3a1 	ldur	w1, [x29, #138]
  4008e8:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  4008ec:	91354000 	add	x0, x0, #0xd50
  4008f0:	97ffff68 	bl	400690 <printf@plt>
  4008f4:	b848e3a1 	ldur	w1, [x29, #142]
  4008f8:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  4008fc:	9135c000 	add	x0, x0, #0xd70
  400900:	97ffff64 	bl	400690 <printf@plt>
  400904:	794127a0 	ldrh	w0, [x29, #146]
  400908:	2a0003e1 	mov	w1, w0
  40090c:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400910:	91364000 	add	x0, x0, #0xd90
  400914:	97ffff5f 	bl	400690 <printf@plt>
  400918:	79412ba0 	ldrh	w0, [x29, #148]
  40091c:	2a0003e1 	mov	w1, w0
  400920:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400924:	9136c000 	add	x0, x0, #0xdb0
  400928:	97ffff5a 	bl	400690 <printf@plt>
  40092c:	b84963a1 	ldur	w1, [x29, #150]
  400930:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400934:	91374000 	add	x0, x0, #0xdd0
  400938:	97ffff56 	bl	400690 <printf@plt>
  40093c:	b849a3a1 	ldur	w1, [x29, #154]
  400940:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400944:	9137c000 	add	x0, x0, #0xdf0
  400948:	97ffff52 	bl	400690 <printf@plt>
  40094c:	b849e3a1 	ldur	w1, [x29, #158]
  400950:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400954:	91384000 	add	x0, x0, #0xe10
  400958:	97ffff4e 	bl	400690 <printf@plt>
  40095c:	b84a23a1 	ldur	w1, [x29, #162]
  400960:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400964:	9138c000 	add	x0, x0, #0xe30
  400968:	97ffff4a 	bl	400690 <printf@plt>
  40096c:	b84a63a1 	ldur	w1, [x29, #166]
  400970:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400974:	91394000 	add	x0, x0, #0xe50
  400978:	97ffff46 	bl	400690 <printf@plt>
  40097c:	b84aa3a1 	ldur	w1, [x29, #170]
  400980:	90000000 	adrp	x0, 400000 <_init-0x5d0>
  400984:	9139c000 	add	x0, x0, #0xe70
  400988:	97ffff42 	bl	400690 <printf@plt>
  40098c:	b849a3a0 	ldur	w0, [x29, #154]
  400990:	2a0003e1 	mov	w1, w0
  400994:	d1000421 	sub	x1, x1, #0x1
  400998:	f90063a1 	str	x1, [x29, #192]
  40099c:	2a0003e1 	mov	w1, w0
  4009a0:	aa0103f9 	mov	x25, x1
  4009a4:	d280001a 	mov	x26, #0x0                   	// #0
  4009a8:	d37dff21 	lsr	x1, x25, #61
  4009ac:	d37df356 	lsl	x22, x26, #3
  4009b0:	aa160036 	orr	x22, x1, x22
  4009b4:	d37df335 	lsl	x21, x25, #3
  4009b8:	2a0003e1 	mov	w1, w0
  4009bc:	aa0103f7 	mov	x23, x1
  4009c0:	d2800018 	mov	x24, #0x0                   	// #0
  4009c4:	d37dfee1 	lsr	x1, x23, #61
  4009c8:	d37df314 	lsl	x20, x24, #3
  4009cc:	aa140034 	orr	x20, x1, x20
  4009d0:	d37df2f3 	lsl	x19, x23, #3
  4009d4:	2a0003e0 	mov	w0, w0
  4009d8:	91003c00 	add	x0, x0, #0xf
  4009dc:	d344fc00 	lsr	x0, x0, #4
  4009e0:	d37cec00 	lsl	x0, x0, #4
  4009e4:	cb2063ff 	sub	sp, sp, x0
  4009e8:	910003e0 	mov	x0, sp
  4009ec:	91000000 	add	x0, x0, #0x0
  4009f0:	f9005fa0 	str	x0, [x29, #184]
  4009f4:	f9405fa0 	ldr	x0, [x29, #184]
  4009f8:	b849a3a1 	ldur	w1, [x29, #154]
  4009fc:	2a0103e1 	mov	w1, w1
  400a00:	aa0103e2 	mov	x2, x1
  400a04:	aa0003e1 	mov	x1, x0
  400a08:	b940d7a0 	ldr	w0, [x29, #212]
  400a0c:	97ffff1d 	bl	400680 <read@plt>
  400a10:	b940d7a0 	ldr	w0, [x29, #212]
  400a14:	97ffff0b 	bl	400640 <close@plt>
  400a18:	52800200 	mov	w0, #0x10                  	// #16
  400a1c:	79012ba0 	strh	w0, [x29, #148]
  400a20:	b848a3a1 	ldur	w1, [x29, #138]
  400a24:	b848e3a0 	ldur	w0, [x29, #142]
  400a28:	1b007c20 	mul	w0, w1, w0
  400a2c:	11006c00 	add	w0, w0, #0x1b
  400a30:	531f7800 	lsl	w0, w0, #1
  400a34:	b807a3a0 	stur	w0, [x29, #122]
  400a38:	b848a3a1 	ldur	w1, [x29, #138]
  400a3c:	b848e3a0 	ldur	w0, [x29, #142]
  400a40:	1b007c20 	mul	w0, w1, w0
  400a44:	531f7800 	lsl	w0, w0, #1
  400a48:	b809a3a0 	stur	w0, [x29, #154]
  400a4c:	9101e3a0 	add	x0, x29, #0x78
  400a50:	d28006c2 	mov	x2, #0x36                  	// #54
  400a54:	aa0003e1 	mov	x1, x0
  400a58:	b940d3a0 	ldr	w0, [x29, #208]
  400a5c:	97ffff01 	bl	400660 <write@plt>
  400a60:	f9005bbf 	str	xzr, [x29, #176]
  400a64:	b900dbbf 	str	wzr, [x29, #216]
  400a68:	14000036 	b	400b40 <main+0x3a4>
  400a6c:	b900dfbf 	str	wzr, [x29, #220]
  400a70:	1400002d 	b	400b24 <main+0x388>
  400a74:	f9405fa2 	ldr	x2, [x29, #184]
  400a78:	b848a3a1 	ldur	w1, [x29, #138]
  400a7c:	b940dba0 	ldr	w0, [x29, #216]
  400a80:	1b007c21 	mul	w1, w1, w0
  400a84:	b940dfa0 	ldr	w0, [x29, #220]
  400a88:	0b000021 	add	w1, w1, w0
  400a8c:	2a0103e0 	mov	w0, w1
  400a90:	531f7800 	lsl	w0, w0, #1
  400a94:	0b010000 	add	w0, w0, w1
  400a98:	2a0003e0 	mov	w0, w0
  400a9c:	8b000040 	add	x0, x2, x0
  400aa0:	f9005ba0 	str	x0, [x29, #176]
  400aa4:	f9405ba0 	ldr	x0, [x29, #176]
  400aa8:	91000800 	add	x0, x0, #0x2
  400aac:	39400000 	ldrb	w0, [x0]
  400ab0:	53037c00 	lsr	w0, w0, #3
  400ab4:	12001c00 	and	w0, w0, #0xff
  400ab8:	53155000 	lsl	w0, w0, #11
  400abc:	13003c01 	sxth	w1, w0
  400ac0:	f9405ba0 	ldr	x0, [x29, #176]
  400ac4:	91000400 	add	x0, x0, #0x1
  400ac8:	39400000 	ldrb	w0, [x0]
  400acc:	53027c00 	lsr	w0, w0, #2
  400ad0:	12001c00 	and	w0, w0, #0xff
  400ad4:	531b6800 	lsl	w0, w0, #5
  400ad8:	13003c00 	sxth	w0, w0
  400adc:	2a000020 	orr	w0, w1, w0
  400ae0:	13003c01 	sxth	w1, w0
  400ae4:	f9405ba0 	ldr	x0, [x29, #176]
  400ae8:	39400000 	ldrb	w0, [x0]
  400aec:	53037c00 	lsr	w0, w0, #3
  400af0:	12001c00 	and	w0, w0, #0xff
  400af4:	13003c00 	sxth	w0, w0
  400af8:	2a000020 	orr	w0, w1, w0
  400afc:	13003c00 	sxth	w0, w0
  400b00:	7900efa0 	strh	w0, [x29, #118]
  400b04:	9101dba0 	add	x0, x29, #0x76
  400b08:	d2800042 	mov	x2, #0x2                   	// #2
  400b0c:	aa0003e1 	mov	x1, x0
  400b10:	b940d3a0 	ldr	w0, [x29, #208]
  400b14:	97fffed3 	bl	400660 <write@plt>
  400b18:	b940dfa0 	ldr	w0, [x29, #220]
  400b1c:	11000400 	add	w0, w0, #0x1
  400b20:	b900dfa0 	str	w0, [x29, #220]
  400b24:	b848a3a1 	ldur	w1, [x29, #138]
  400b28:	b940dfa0 	ldr	w0, [x29, #220]
  400b2c:	6b00003f 	cmp	w1, w0
  400b30:	54fffa28 	b.hi	400a74 <main+0x2d8>  // b.pmore
  400b34:	b940dba0 	ldr	w0, [x29, #216]
  400b38:	11000400 	add	w0, w0, #0x1
  400b3c:	b900dba0 	str	w0, [x29, #216]
  400b40:	b848e3a1 	ldur	w1, [x29, #142]
  400b44:	b940dba0 	ldr	w0, [x29, #216]
  400b48:	6b00003f 	cmp	w1, w0
  400b4c:	54fff908 	b.hi	400a6c <main+0x2d0>  // b.pmore
  400b50:	b940d3a0 	ldr	w0, [x29, #208]
  400b54:	97fffebb 	bl	400640 <close@plt>
  400b58:	52800000 	mov	w0, #0x0                   	// #0
  400b5c:	9100037f 	mov	sp, x27
  400b60:	910003bf 	mov	sp, x29
  400b64:	a94153f3 	ldp	x19, x20, [sp, #16]
  400b68:	a9425bf5 	ldp	x21, x22, [sp, #32]
  400b6c:	a94363f7 	ldp	x23, x24, [sp, #48]
  400b70:	a9446bf9 	ldp	x25, x26, [sp, #64]
  400b74:	f9402bfb 	ldr	x27, [sp, #80]
  400b78:	a8ce7bfd 	ldp	x29, x30, [sp], #224
  400b7c:	d65f03c0 	ret

0000000000400b80 <__libc_csu_init>:
  400b80:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400b84:	910003fd 	mov	x29, sp
  400b88:	a901d7f4 	stp	x20, x21, [sp, #24]
  400b8c:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x10174>
  400b90:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x10174>
  400b94:	91374294 	add	x20, x20, #0xdd0
  400b98:	913722b5 	add	x21, x21, #0xdc8
  400b9c:	a902dff6 	stp	x22, x23, [sp, #40]
  400ba0:	cb150294 	sub	x20, x20, x21
  400ba4:	f9001ff8 	str	x24, [sp, #56]
  400ba8:	2a0003f6 	mov	w22, w0
  400bac:	aa0103f7 	mov	x23, x1
  400bb0:	9343fe94 	asr	x20, x20, #3
  400bb4:	aa0203f8 	mov	x24, x2
  400bb8:	97fffe86 	bl	4005d0 <_init>
  400bbc:	b4000194 	cbz	x20, 400bec <__libc_csu_init+0x6c>
  400bc0:	f9000bb3 	str	x19, [x29, #16]
  400bc4:	d2800013 	mov	x19, #0x0                   	// #0
  400bc8:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400bcc:	aa1803e2 	mov	x2, x24
  400bd0:	aa1703e1 	mov	x1, x23
  400bd4:	2a1603e0 	mov	w0, w22
  400bd8:	91000673 	add	x19, x19, #0x1
  400bdc:	d63f0060 	blr	x3
  400be0:	eb13029f 	cmp	x20, x19
  400be4:	54ffff21 	b.ne	400bc8 <__libc_csu_init+0x48>  // b.any
  400be8:	f9400bb3 	ldr	x19, [x29, #16]
  400bec:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400bf0:	a942dff6 	ldp	x22, x23, [sp, #40]
  400bf4:	f9401ff8 	ldr	x24, [sp, #56]
  400bf8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400bfc:	d65f03c0 	ret

0000000000400c00 <__libc_csu_fini>:
  400c00:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400c04 <_fini>:
  400c04:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400c08:	910003fd 	mov	x29, sp
  400c0c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400c10:	d65f03c0 	ret
